Jan Ernst, Normal Computing

DRAMBench: Autoformalizing DRAM Specifications with Timed Petri Nets

Chip design verification is dominated by manual interpretation of complex DRAM standards. With DRAMPyML and DRAMBench, Fraunhofer IESE and Normal Computing introduce timed Petri net models and an open benchmark to autoformalize memory specifications. This post shows how AI can bridge the gap between natural language specs and formal verification artifacts. Co-authorDr. Jan Ole Ernst…

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